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| Datasheet File OCR Text: |
| M29W128GH M29W128GL 128 Mbit (16 Mb x 8 or 8 Mb x 16, page, uniform block) 3 V supply Flash memory Features Supply voltage - VCC = 2.7 to 3.6 V for Program, Erase and Read - VCCQ = 1.65 to 3.6 V for I/O buffers - VPPH = 12 V for Fast Program (optional) Asynchronous Random/Page Read - Page size: 8 words or 16 bytes - Page access: 25, 30 ns - Random access: 60 (only available upon customer request) or 70, 80 ns Fast Program commands - 32 words (64-byte write buffer) Enhanced Buffered Program commands - 256 words Programming time - 16 s per byte/word typical - Chip program time: 5 s with VPPH and 8 s without VPPH Memory organization - M29128GH/L: 128 main blocks, 128 Kbytes/64 Kwords each Program/Erase controller - Embedded byte/word program algorithms Program/ Erase Suspend and Resume - Read from any block during Program Suspend - Read and Program another block during Erase Suspend TSOP56 (N) 14 x 20 mm BGA TBGA64 (ZA) 10 x 13 mm - Faster Production/Batch Programming - Faster Block and Chip Erase VPP/WP pin for Fast Program and Write: protects first or last block regardless of block protection settings Software protection: - Volatile protection - Non-volatile protection - Password protection Common Flash interface - 64 bit security code 128 word extended memory block - Extra block used as security block or to store additional information Low power consumption - Standby and automatic standby Minimum 100,000 Program/Erase cycles per block ECOPACK(R) packages Unlock Bypass/Block Erase/Chip Erase/Write to Buffer/Enhanced Buffered Program commands Table 1. Device summary Root part number M29W128GH: uniform, last block protected by VPP/WP M29W128GL: uniform, first block protected by VPP/WP Device code 227Eh + 2221h + 2201h 227Eh + 2221h + 2200h March 2008 Rev 4 1/94 www.numonyx.com 1 Contents M29W128GH, M29W128GL Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data inputs/outputs or address inputs (DQ15A-1) . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Byte/word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auto Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.1 3.7.2 3.7.3 3.7.4 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Verify extended memory block protection indicator . . . . . . . . . . . . . . . . 19 Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/94 M29W128GH, M29W128GL Contents 5 Software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Non-volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 5.2.2 Non-volatile protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Non-volatile Protection Bit Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 Write to Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Enhanced Buffered Program command . . . . . . . . . . . . . . . . . . . . . . . . . 35 Buffered Program Abort and Reset command . . . . . . . . . . . . . . . . . . . . 36 Write to Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . . . 37 Enhanced Buffered Program Confirm command . . . . . . . . . . . . . . . . . . 37 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Unlock Bypass Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . 38 Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . . 38 Unlock Bypass Enhanced Buffered Program command . . . . . . . . . . . . 38 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.1 6.3.2 6.3.3 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 42 Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . . 42 Lock Register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3/94 Contents 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 M29W128GH, M29W128GL Password Protection mode command set . . . . . . . . . . . . . . . . . . . . . . . 43 Non-volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . . 44 NVPB Lock Bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 46 Exit Protection command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1 7.1.2 7.1.3 7.1.4 Password Protection Mode Lock bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . 51 Non-volatile Protection Mode Lock bit (DQ1) . . . . . . . . . . . . . . . . . . . . . 51 Extended Block Protection bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DQ15 to DQ3 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3 Buffered Program Abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 9 10 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Appendix A Block addresses and read/modify protection groups . . . . . . . . . . 78 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 C.1 C.2 Factory locked extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Customer lockable extended memory block . . . . . . . . . . . . . . . . . . . . . . . 88 Appendix D Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4/94 M29W128GH, M29W128GL Contents 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5/94 List of tables M29W128GH, M29W128GL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VPP/WP functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus operations, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read electronic signature - auto select mode - programmer method (8-bit mode) . . . . . . 21 Read electronic signature - auto select mode - programmer method (16-bit mode) . . . . . 21 Block protection - auto select mode - programmer method (8-bit mode) . . . . . . . . . . . . . . 22 Block protection - auto select mode - programmer method (16-bit mode) . . . . . . . . . . . . . 22 Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Enhanced Buffered Program commands, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Program, Erase times and Program, Erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 50 Lock Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Accelerated Program and Data Polling/Data Toggle AC characteristics . . . . . . . . . . . . . . 74 TSOP56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data . . . . 75 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data. . . . 76 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6/94 M29W128GH, M29W128GL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 NVPB Program/Erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Lock Register program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Random Read AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Random Read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Page Read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 66 Write Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . 67 Chip Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chip Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 70 Chip/Block Erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Reset AC waveforms (no program/erase ongoing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Reset during program/erase operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data polling AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Toggle/Alternative Toggle bit polling AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . 74 TSOP56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . . . . . . 75 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline . . . . . . . . . . . 76 Write to Buffer Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Enhanced Buffered Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7/94 Description M29W128GH, M29W128GL 1 Description The M29W128GH and M29W128GL are 128 Mbit (8 Mb x 16 or 16 Mb x 8) non-volatile Flash memories that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its Read mode. The memory array is divided into 64-Kword/128-Kbyte uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the command interface of the memory. An on-chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The M29W128GH and M29W128GL support Asynchronous Random Read and Page Read from all blocks of the memory array. The devices also feature a Write to Buffer Program capability that improves the programming throughput by programming in one shot a buffer of 32 words/64 bytes. The Enhanced Buffered Program feature is also available to speed up the programming throughput, allowing to program 256 words in one shot (only in x 16 mode). The VPP/WP signal can be used to enable faster programming of the device. The M29W128GH and M29W128GL have an extra block, the extended block, of 128 words in x 16 mode or of 256 bytes in x 8 mode that can be accessed using a dedicated command. The extended block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. The device features different levels of hardware and software block protection to avoid unwanted program or erase (modify): Hardware protection: - The VPP/WP provides a hardware protection of the highest and lowest block on the M29W128GH, M29W128GL, respectively. Volatile protection Non-volatile protection Password protection Software protection: - - - The M29W128GH and M29W128GL are offered in TSOP56 (14 x 20 mm), and TBGA64 (10 x 13 mm, 1 mm pitch), packages. The memories are delivered with all the bits erased (set to `1'). 8/94 M29W128GH, M29W128GL Table 2. Signal names Name A0-A22 DQ0-DQ7 DQ8-DQ14 DQ15A- 1 E G W RP RB BYTE VCCQ VCC VPP/WP(1) VSS NC Address inputs Data inputs/outputs Data inputs/outputs Data input/output or address input Chip Enable Output Enable Write Enable Reset Ready/Busy output Byte/word organization select Input/output buffer supply voltage Supply voltage VPP/Write Protect Ground Not connected Description Description Direction Inputs I/O I/O I/O Input Input Input Input Output Input Supply Supply Input - 1. VPP/WP may be left floating as it is internally connected to a pull-up resistor which enables Program/Erase operations. Figure 1. Logic diagram VCC VCCQ VPP/WP 23 A0-A22 W E G RP BYTE M29W128GH M29W128GL 15 DQ0-DQ14 DQ15A-1 RB VSS AI13330b 1. Also see Appendix A and Table 34 for a full listing of the block addresses. 9/94 Description Figure 2. TSOP connections NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 56 NC NC A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC VCCQ M29W128GH, M29W128GL 14 43 M29W128GH 15 M29W128GL 42 28 29 AI13331 10/94 M29W128GH, M29W128GL Figure 3. TBGA connections (top view through package) 1 2 3 4 5 6 7 8 Description A NC A3 A7 RB W A9 A13 NC B NC A4 A17 VPP/WP RP A8 A12 A22 C NC A2 A6 A18 A21 A10 A14 NC D NC A1 A5 A20 A19 A11 A15 VCCQ E NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS F VCCQ E DQ8 DQ10 DQ12 DQ14 BYTE NC G NC G DQ9 DQ11 VCC DQ13 DQ15 A-1 NC H NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC AI11527c 11/94 Description Figure 4. Block addresses (x 8) Address lines A22-A0, DQ15A-1 (x 16) Address lines A22-A0 M29W128GH, M29W128GL FFFFFFh 128 Kbytes 7FFFFFh 64 Kwords Total of 128 uniform blocks 01FFFFh 128 Kbytes 010000h 00FFFFh 128 Kbytes 000000h 000000h AI13332 64 Kwords 007FFFh 64 Kwords 12/94 M29W128GH, M29W128GL Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A22) The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the command interface of the internal state machine. 2.3 Data inputs/outputs (DQ8-DQ14) The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. 2.4 Data inputs/outputs or address inputs (DQ15A- 1) When the device is in x 16 bus mode, this pin behaves as a Data input/output pin (as DQ8DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant bit of the address. Throughout the text consider references to the Data input/output to include this pin when the device operates in x 16 bus mode and references to the Address inputs to include this pin when the device operates in x 8 bus mode except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.6 Output Enable (G) The Output Enable pin, G, controls the Bus Read operation of the memory. 13/94 Signal descriptions M29W128GH, M29W128GL 2.7 Write Enable (W) The Write Enable pin, W, controls the Bus Write operation of the memory's command interface. 2.8 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin provides two functions. The VPPH function allows the memory to use an external high voltage power supply to reduce the time required for program operations. This is achieved by bypassing the unlock cycles. The Write Protect function provides a hardware method of protecting the highest or lowest block (see Section 1: Description). When VPP/Write Protect is Low, VIL, the highest or lowest block is protected. Program and Erase operations on this block are ignored while VPP/Write Protect is Low. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the highest or lowest block. Program and Erase operations can now modify the data in this block unless the block is protected using Block protection. When VPP/Write Protect is raised to VPPH the memory automatically enters the Unlock Bypass mode (see Section 6.2.6). When VPP/Write Protect is raised to VPPH, the execution time of the command is lower (see Table 17: Program, Erase times and Program, Erase endurance cycles). When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the command interface section. The transitions from VIH to VPPH and from VPPH to VIH must be slower than tVHVPP (see Figure 23: Accelerated program timing waveforms). Never raise VPP/Write Protect to VPPH from any mode except Read mode, otherwise the memory may be left in an indeterminate state. A 0.1 F capacitor should be connected between the VPP/Write Protect pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program (see IPP1, IPP2, IPP3, IPP4 in Table 25: DC characteristics). The VPP/Write Protect pin may be left floating or unconnected because it features an internal pull-up. Refer to Table 3 for a summary of VPP/WP functions. Table 3. VPP/WP functions Function Highest block protected on M29W128GH. Lowest block protected on M29W128GL. Highest and lowest block unprotected unless a software protection is activated (see Section 4: Hardware protection). Unlock bypass mode. It supplies the current needed to speed up programming. VPP/WP VIL VIH VPPH 14/94 M29W128GH, M29W128GL Signal descriptions 2.9 Reset (RP) The Reset pin can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset Low, VIL, for at least tPLPX. After Reset goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.10: Ready/Busy output (RB), Table 29: Reset AC characteristics, Figure 21 and Figure 22 for more details. 2.10 Ready/Busy output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. During program or erase operations Ready/Busy is Low, VOL (see Table 20: Status Register bits). Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 29: Reset AC characteristics, Figure 21 and Figure 22. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/word organization select (BYTE) It is used to switch between the x 8 and x 16 Bus modes of the memory. When Byte/word organization select is Low, VIL, the memory is in x 8 mode, when it is High, VIH, the memory is in x 16 mode. 2.12 VCC supply voltage VCC provides the power supply for all operations (Read, Program and Erase). The command interface is disabled when the VCC supply voltage is less than the Lockout voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power-up, power-down and power surges. If the Program/Erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 F capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations (see ICC1, ICC2, ICC3 in Table 25: DC characteristics). 2.13 VCCQ input/output supply voltage VCCQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VCC. 15/94 Signal descriptions M29W128GH, M29W128GL 2.14 Vss ground VSS is the reference for all voltage measurements. The device features two VSS pins both of which must be connected to the system ground. 16/94 M29W128GH, M29W128GL Bus operations 3 Bus operations There are five standard bus operations that control the device. These are Bus Read (Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby. See Table 4: Bus operations, 8-bit mode and Table 5: Bus operations, 16-bit mode for a summary. Typical glitches of less than 5 ns on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the command interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The page has a size of 8 words (or 16 bytes) and is addressed by the address inputs A2-A0 in x 16 mode and A2-A0 plus DQ15A- in byte mode. 1 A valid Bus Read operation involves setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data inputs/outputs will output the value, see Figure 13: Random Read AC waveforms (8-bit mode), Figure 15: Page Read AC waveforms (16-bit mode), and Table 26: Read AC characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write to the command interface. A valid Bus Write operation begins by setting the desired address on the Address inputs. The Address inputs are latched by the command interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data inputs/outputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 16, and Figure 17, Write AC waveforms, and Table 27 and Table 28, Write AC characteristics, for details of the timing requirements. 3.3 Output Disable The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby Driving Chip Enable High in Read mode, causes the memory to enter Standby mode and the data inputs/outputs pins are placed in the high-impedance state. To reduce the Supply current to the Standby Supply current, ICC2, Chip Enable should be held within VCC 0.3 V. For the Standby current level see Table 25: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply current, ICC3, for Program or Erase operations until the operation completes. 17/94 Bus operations M29W128GH, M29W128GL 3.5 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when RP is at VIL. The power consumption is reduced to the standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. 3.6 Automatic Standby Automatic Standby allows the memory to achieve low power consumption during Read mode. After a read operation, if CMOS levels (VCC 0.3 V) are used to drive the bus and the bus is inactive for tAVQV + 30 ns or more, the memory enters Automatic Standby where the internal Supply current is reduced to the Standby Supply current, ICC2 (see Table 25: DC characteristics). The Data inputs/outputs will still output data if a Bus Read operation is in progress. The power supplier of data bus, VCCQ, can have a null consumption (depending on load circuits connected with data bus) when the memory enters Automatic Standby. 3.7 Auto Select mode The Auto Select mode allows the system or the programming equipment to read the electronic signature, verify the protection status of the extended memory block, and apply/remove Block protection. For example, this mode can be used by a programming equipment to automatically match a device and the application code to be programmed. There are two methods to enter Auto Select mode: programmer method: Additional bus operations are used. They require VID to be applied to address pin A9. Refer to Table 6, Table 7, Table 8, and Table 9 for a description of the bus operations required to read the electronic signature using the programmer method in-system method: The Auto Select mode is entered by issuing the Auto Select command (see Section 6.1.2). It is not necessary to apply VID to A9. At power-up, the device is in Read mode, and can then be put in Auto Select mode by using one of the methods described above. The device cannot enter Auto Select mode when a program or erase operation is ongoing (RB Low). However, Auto Select mode can be entered if the erase operation has been suspended by issuing an Erase Suspend command (see Section 6.1.6). The Auto Select mode is exited by performing a reset. The device is returned to Read mode, except if the Auto Select mode was entered after an Erase Suspend or a Program Suspend command. In this case, it returns to the Erase or Program Suspend mode. 3.7.1 Read electronic signature The memory has two codes, the manufacturer code and the device code used to identify the memory. These codes can be accessed by performing read operations with control signals and addresses set as shown in Table 6: Read electronic signature - auto select mode - 18/94 M29W128GH, M29W128GL Bus operations programmer method (8-bit mode) and Table 7: Read electronic signature - auto select mode - programmer method (16-bit mode). These codes can also be accessed by issuing an Auto Select command (see Section 6.1.2: Auto Select command). 3.7.2 Verify extended memory block protection indicator The extended memory block is either factory locked or customer lockable. The protection status of the extended memory block (factory locked or customer lockable) can be accessed by reading the extended memory block protection indicator. It can be read in Auto Select mode using either the programmer (see Table 8 and Table 9) or the in-system method (see Table 10 and Table 11). The protection status of the extended memory block is then output on bit DQ7 of the Data input/outputs (see Table 4 and Table 5, Bus operations in 8-bit and 16-bit mode). 3.7.3 Verify block protection status The protection status of a block can be directly accessed by performing a read operation with control signals and addresses set as shown in Table 8 and Table 9. If the block is protected, then 01h (in x 8 mode) is output on Data input/outputs DQ0-DQ7, otherwise 00h is output. 3.7.4 Hardware Block Protect The VPP/WP pin can be used to protect the highest or lowest block. When VPP/WP is at VIL the highest (M29W128GH) or lowest block (M29W128GL) is protected and remains protected regardless of the block protection status or the Reset pin state. 19/94 Bus operations Table 4. Bus operations, 8-bit mode Address Inputs E VIL VIL VIH VIL X G VIL VIH X VIH X W VIH VIL X VIH X RP VIH VIH VIH VIH VIL VPP/WP A22-A0, DQ15A-1 Bus Read Bus Write Standby Output Disable Reset 1. X = VIL or VIH. 2. If WP is Low, VIL, the outermost block remains protected. M M29W128GH, M29W128GL Operation(1) Data inputs/outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data output Data input(3) Hi-Z Hi-Z Hi-Z X VIH(2) VIH X X Cell address Command address X X X 3. Data input as required when issuing a command sequence, performing data polling or block protection. Table 5. Bus operations, 16-bit mode Address inputs E VIL VIL VIH VIL X G VIL VIH X W VIH VIL X RP VPP/WP A22-A0 DQ15A-1, DQ14-DQ0 Data output Data input(3) Hi-Z Hi-Z Hi-Z VIH VIH VIH VIH VIL X VIH(2) VIH X X Cell address Command address X X X Data inputs/outputs Operation(1) Bus Read Bus Write Standby Output Disable Reset 1. X = VIL or VIH. VIH VIH X X 2. If WP is Low, VIL, the outermost block remains protected. 3. Data input as required when issuing a command sequence, performing data polling or block protection. 20/94 M29W128GH, M29W128GL Table 6. Read cycle(1) Manufacturer code Device code (cycle 1) Device code (cycle 2) Device code (cycle 3) 1. X = VIL or VIH. 2. When using the in-system method, applying VID to A9 is not required. A9 can be either VIL or VIH. Bus operations Read electronic signature - auto select mode - programmer method (8-bit mode) Address inputs EGW A22-A10 A9 A8A7 Data inputs/outputs DQ7-DQ0 20h 7Eh (both devices) 21h (both devices) 01h (M29W128GH) 00h (M29W128GL) A6 A5-A4 A3 A2 A1 A0 DQ15A-1 DQ14-DQ8 VIL VIL VIL VIL VIL VIL VIL VIH X X X X X X X X VIL VIL VIH X VID (2) X VIL X VIH VIH VIH VIL VIH VIH VIH VIH Table 7. Read cycle(1) Manufacturer code Device code (cycle 1) Device code (cycle 2) Device code (cycle 3) Read electronic signature - auto select mode - programmer method (16-bit mode) Address inputs E G W A22-A10 A9 A8-A7 A6 A5-A4 A3 VIL VIL VIL VIL VIH X VID (2) Data inputs/outputs A2 VIL VIL A1 VIL A0 VIL DQ15A-1, DQ14-DQ0 0020h 227Eh (both devices) 2221h (both devices) 2201h (M29W128GH) 2200h (M29W128GL) VIL VIH X VIL X VIH VIH VIH VIL VIH VIH VIH VIH 1. X = VIL or VIH. 2. When using the in-system method, applying VID to A9 is not required. A9 can be either VIL or VIH. 21/94 Bus operations Table 8. M29W128GH, M29W128GL Block protection - auto select mode - programmer method (8-bit mode) Address inputs Data inputs/outputs DQ7-DQ0 89h (factory locked) 09h (customer lockable) X M29W128GH VIL VIL VIH X VID (2) Operation(1) E G W DQ15 DQ14 A5- A3A8A22- A14A1 A0 A6 A9 A-1 -DQ8 A4 A2 A7 A16 A10 Verify extended memory block protection indicator (bit DQ7) M29W128GL VIH X VIL X VIL VIH X X 99h (factory locked) 19h (customer lockable) Verify block protection status BAd VIL 01h (protected) 00h (unprotected) 1. X = VIL or VIH. BAd any address in the block. 2. When using the in-system method, applying VID to A9 is not required. A9 can be either VIL or VIH. Table 9. Block protection - auto select mode - programmer method (16-bit mode) Address inputs Data inputs/outputs A3A2 A1 A0 DQ15A-1, DQ14-DQ0 0089h (factory locked) 0009h (customer lockable) X M29W128GH VIL VIL VIH X VID (2) Operation(1) E G W A22A16 A14A10 A9 A8A6 A7 A5A4 Verify extended memory block indicator (bit DQ7) M29W128GL VIH X VIL X VIL VIH 0099h (factory locked) 0019h (customer lockable) 0001h (protected) 0000h (unprotected) Verify block protection status BAd VIL 1. X = VIL or VIH. BAd any address in the block. 2. When using the in-system method, applying VID to A9 is not required. A9 can be either VIL or VIH. 22/94 M29W128GH, M29W128GL Hardware protection 4 Hardware protection The M29W128GH and M29W128GL feature a VPP/WP pin that protects the highest or lowest block. Refer to Section 2: Signal descriptions for a detailed description of the signal. 5 Software protection The M29W128GH and M29W128GL have three different software protection modes: Volatile protection Non-volatile protection Password protection On first use all parts default to operate in non-volatile protection mode and the customer is free to activate the non-volatile or the password protection mode. The desired protection mode is activated by setting either the one-time programmable Nonvolatile Protection Mode Lock bit, or the Password Protection Mode Lock bit of the Lock Register (see Section 7.1: Lock Register). Programming the Non-volatile Protection Mode Lock bit or the Password Protection Mode Lock bit, to `0' will permanently activate the Nonvolatile or the Password Protection mode, respectively. These two bits are one-time programmable and non-volatile: once the protection mode has been programmed, it cannot be changed and the device will permanently operate in the selected protection mode. It is recommended to activate the desired software protection mode when first programming the device. The Non-volatile and Password Protection modes both provide non-volatile protection. Volatilely protected blocks and non-volatilely protected blocks can co-exist within the memory array. However, the volatile protection only control the protection scheme for blocks that are not protected using the non-volatile or password protection. If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. The device is shipped with all blocks unprotected. The block protection status can be read either by performing a read electronic signature (see Table 6 and Table 7) or by issuing an Auto Select command (see Table 19: Block protection status). For the lowest and highest blocks, an even higher level of block protection can be achieved by locking the blocks using the non-volatile protection and then by holding the VPP/WP pin Low. 23/94 Software protection M29W128GH, M29W128GL 5.1 Volatile protection mode The volatile protection allows the software application to easily protect blocks against inadvertent change. However, the protection can be easily disabled when changes are needed. Volatile Protection bits, VPBs, are volatile and unique for each block and can be individually modified. VPBs only control the protection scheme for unprotected blocks that have their non-volatile protection bits, NVPBs, cleared (erased to `1') (see Section 5.2: Nonvolatile protection mode and Section 6.3.5: Non-volatile Protection mode command set). By issuing the VPB Program or VPB Clear commands, the VPBs are set (programmed to `0') or cleared (erased to `1'), thus placing each block in the protected or unprotected state respectively. The VPBs can be set (programmed to `0') or cleared (erased to `1') as often as needed. When the parts are first shipped, or after a power-up or hardware reset, the VPBs can be set or cleared depending upon the ordering option chosen: If the option to clear the VPBs after power-up is selected, then the blocks can be programmed or erased depending on the NVPBs state (see Table 19: Block protection status) If the option to set the VPBs after power-up is selected, the blocks default to be protected. Refer to Section 6.3.7 for a description of the volatile protection mode command set. 5.2 5.2.1 Non-volatile protection mode Non-volatile protection bits A non-volatile protection bit (NVPB) is assigned to each block. When a NVPB is set to `0', the associated block is protected, preventing any program or erase operations in this block. The NVPB bits are set individually by issuing a NVPB Program command. They are nonvolatile and will remain set through a hardware reset or a power-down/power-up sequence. The NVPBs cannot be cleared individually, they can only be cleared all at the same time by issuing a Clear all Non-volatile Protection bits command. The NVPBs can be protected all at a time by setting a volatile bit, the NVPB Lock bit (see Section 5.2.2: Non-volatile Protection Bit Lock bit). If one of the non-volatile protected blocks needs to be unprotected (corresponding NVPB set to `1'), a few more steps are required: 1. 2. 3. First, the NVPB Lock bit must be cleared by either putting the device through a power cycle, or hardware reset The NVPBs can then be changed to reflect the desired settings The NVPB Lock bit must be set once again to lock the NVPBs. The device operates normally again. Note: 1 2 To achieve the best protection, it is recommended to execute the NVPB Lock Bit Program command early in the boot code and to protect the boot code by holding VPP/WP Low, VIL. The NVPBs and VPBs have the same function when VPP/WP pin is High, VIH, as they do when VPP /WP pin is at the voltage for program acceleration (VPPH). 24/94 M29W128GH, M29W128GL Software protection Refer to Table 19: Block protection status and Figure 5: Software protection scheme for details on the block protection mechanism, and to Section 6.3.5 for a description of the Nonvolatile Protection mode command set. 5.2.2 Non-volatile Protection Bit Lock bit The Non-volatile Protection Bit Lock bit (NVPB Lock bit) is a global volatile bit for all blocks. When set (programmed to `0'), it prevents changing the state of the NVPBs. When cleared (programmed to `1'), the NVPBs can be set and reset using the NVPB Program command and Clear all NVPBs command, respectively. There is only one NVPB Lock bit per device. Refer to Section 6.3.6 for a description of the NVPB Lock bit command set. Note: 1 2 No software command unlocks this bit unless the device is in password protection mode; it can be cleared only by taking the device through a hardware reset or a power-up. The NVPB Lock bit must be set (programmed to `0') only after all NVPBs are configured to the desired settings. 5.3 Password protection mode The password protection mode provides an even higher level of security than the Nonvolatile Protection mode by requiring a 64-bit password for unlocking the device NVPB Lock bit. In addition to this password requirement, the NVPB Lock bit is set `0' after power-up and reset to maintain the device in password protection mode. Successful execution of the Password Unlock command by entering the correct password clears the NVPB Lock bit, allowing for block NVPBs to be modified. If the password provided is not correct, the NVPL Lock bit remains locked and the state of the NVPBs cannot be modified. To place the device in password protection mode, the following steps are required: 1. Prior to entering the password protection mode, it is necessary to set a 64-bit password and to verify it (see Password Program command and Password Read command). Password verification is only allowed during the password programming operation The password protection mode is then activated by programming the Password Protection Mode Lock bit to `0'. This operation is not reversible and once the bit is programmed it cannot be erased, the device permanently remains in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. Moreover, all commands to the address where the password is stored, are disabled. Refer to Table 19: Block protection status and Figure 5: Software protection scheme for details on the block protection scheme. 2. Refer to Section 6.3.4 for a description of the Password Protection mode command set. Note: There is no means to verify the password after it is set. If the password is lost after setting the Password Mode Lock bit, there is no way to clear the NVPB Lock bit. 25/94 Software protection Figure 5. Software protection scheme M29W128GH, M29W128GL Parameter block or main block VPB(2) NVPB(1) Volatile protection Non-volatile protection NVPB Lock bit(3) Non-volatile protection mode Password protection mode AI13676 1. NVPBs default to `1' (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its NVPB is set to `0' and `1', respectively. NVPBs are programmed individually and cleared collectively. 2. VPB default status depends on ordering option. A block is protected or unprotected when its VPB is set to `0' and `1', respectively. VPBs are programmed and cleared individually. For the volatile protection to be effective, the NVPB Lock bit must be set to `0' (NVPB bits unlocked) and the block NVPB must be set to `1' (block unprotected). 3. The NVPB Lock bit is volatile and default to `1' (NVPB bits unlocked) after power-up and hardware reset. NVPB bits are locked by setting the NVPB Lock bit to `0'. Once programmed to `0', the NVPB Lock bit can be reset to `1' only be taking the device through a power-up or hardware reset. 26/94 M29W128GH, M29W128GL Command interface 6 Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. 6.1 Standard commands See either Table 10, or Table 11, depending on the configuration that is being used, for a summary of the standard commands. 6.1.1 Read/Reset command The device is in Read mode after reset or after power-up. The Read/Reset command returns the memory to Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. If the Read/Reset command is issued during the timeout of a Block erase operation, the memory will take up to 10 s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 6.1.2 Auto Select command The Auto Select command puts the device in Auto Select mode, when using the in-system method (see Section 3.7: Auto Select mode). When in Auto Select mode, the system can read the manufacturer code, the device code, the protection status of each block (Block Protection status) and the extended memory block protection indicator. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued Bus Read operations to specific addresses output the manufacturer code, the device code, the extended memory block protection indicator and a block protection status (see Table 10 and Table 11 in conjunction with Table 6, Table 7, Table 8, and Table 9). The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. 27/94 Command interface M29W128GH, M29W128GL 6.1.3 Read CFI Query command The memory contains an information area, named CFI data structure, which contains a description of various electrical and timing parameters, density information and functions supported by the memory. See Appendix B, Table 35, Table 36, Table 37, Table 38, Table 39 and Table 40 for details on the information contained in the common Flash interface (CFI) memory area. The Read CFI Query command is used to put the memory in Read CFI Query mode. Once in Read CFI Query mode, Bus Read operations to the memory will output data from the common Flash interface (CFI) memory area. One Bus Write cycle is required to issue the Read CFI Query command. This command is valid only when the device is in the Read Array or Auto Select mode. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command is required to put the device in Read Array mode from Auto Select mode. 6.1.4 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase command and start the Program/Erase controller. If some block are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical Chip Erase times are given in Table 17. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data inputs/outputs. See Section 7.2: Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. The Chip Erase operation is aborted by performing a reset or powering down the device. In this case, data integrity cannot be ensured, and it is recommended to erase again the entire chip. 6.1.5 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. It sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. After the command sequence is written, a Block Erase timeout occurs. During the timeout period, additional sector addresses and sector erase commands may be written. Once the Program/Erase controller has started, it is not possible to select 28/94 M29W128GH, M29W128GL Command interface any more blocks. Each additional block must therefore be selected within the timeout period of the last block. The timeout timer restarts when an additional block is selected. After the sixth Bus Write operation, a Bus Read operation outputs the Status Register. See Figure 16: Write Enable Controlled Program waveforms (8-bit mode) and Figure 17: Write Enable Controlled Program waveforms (16-bit mode) for details on how to identify if the Program/Erase controller has started the Block Erase operation. After the Block Erase operation has completed, the memory returns to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory ignores all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the timeout period. Typical Block Erase time and Block Erase timeout are given in Table 17. The Block Erase operation is aborted by performing a reset or powering down the device. In this case, data integrity cannot be ensured, and it is recommended to erase again the blocks aborted. 6.1.6 Erase Suspend command The Erase Suspend command can be used to temporarily suspend a Block Erase operation. One Bus Write operation is required to issue the command together with the block address. After the command sequence is written, a minimum Block Erase timeout occurs (see Section 6.1.6: Erase Suspend command). During the timeout period, additional block addresses and block erase commands can be written. The Program/Erase controller suspends the erase operation within the Erase Suspend Latency time of the Erase Suspend command being issued. However, when the Erase Suspend command is written during the Block Erase timeout, the device immediately terminates the timeout period and suspends the erase operation. Once the Program/Erase controller has stopped, the memory operates in Read mode and the Erase is suspended. During Erase Suspend it is possible to read and execute Program or Write to Buffer Program operations in blocks that are not suspended; both read and program operations behave as normal on these blocks. Reading from blocks that are suspended will output the Status Register. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. In this case the Status Register is not read and no error condition is given. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the extended memory block will output the extended memory block data. Once in the Extended Block mode, the Exit Extended Block command must be issued before the erase operation can be resumed. The Erase Suspend command is ignored if written during Chip Erase operations. 29/94 Command interface M29W128GH, M29W128GL Refer to Table 17: Program, Erase times and Program, Erase endurance cycles for the values of Block Erase timeout and Block Erase Suspend latency time. If the Erase Suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to erase again the blocks suspended. 6.1.7 Erase Resume command The Erase Resume command is used to restart the Program/Erase controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. 6.1.8 Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend latency time (see Table 17: Program, Erase times and Program, Erase endurance cycles) and updates the Status Register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from program-suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the extended memory block area (one-time program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. If the Program Suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to program again the words or bytes aborted. 6.1.9 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to Figure 16: Write Enable Controlled Program waveforms (8-bit mode) and Figure 17: Write Enable Controlled Program waveforms (16-bit mode) for details. The system must issue a Program Resume command, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 30/94 M29W128GH, M29W128GL Command interface 6.1.10 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.8: Program Suspend command and Section 6.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. After programming has started, Bus Read operations output the Status Register content. See Figure 16: Write Enable Controlled Program waveforms (8-bit mode) and Figure 17: Write Enable Controlled Program waveforms (16-bit mode) for more details. Typical program times are given in Table 17: Program, Erase times and Program, Erase endurance cycles. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations to the memory continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. The Program operation is aborted by performing a reset or powering-down the device. In this case data integrity cannot be ensured, and it is recommended to reprogram the word or byte aborted. 31/94 Command interface Table 10. Standard commands, 8-bit mode M29W128GH, M29W128GL Bus operations(1) Command Length 1st Add 1 Read/Reset 3 Manufacturer code Device code Auto Select Extended memory block protection indicator Block protection status Program(4) Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 6 6+ 1 1 1 AAA AAA AAA X X AA AA AA AA B0 30 98 555 555 555 55 55 55 AAA AAA AAA A0 80 80 PA AAA AAA PD AA AA 555 555 55 55 AAA BAd 10 30 3 AAA AA 555 55 AAA 90 (2)(3) (2)(3) 2nd 3rd Add 4th 5th 6th Data Add Data F0 AA 555 55 Data Add Data Add Data Add Data X AAA X F0 1. X Don't care, PA Program Address, PD Program Data, BAd Any address in the Block. All values in the table are in hexadecimal. 2. These cells represent Read cycles. The other cells are Write cycles. 3. The Auto Select addresses and data are given in Table 6: Read electronic signature - auto select mode - programmer method (8-bit mode), and Table 8: Block protection - auto select mode - programmer method (8-bit mode), except for A9 that is `Don't care'. 4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 12: Fast Program commands, 8-bit mode and Table 13: Fast Program commands, 16-bit mode). 32/94 M29W128GH, M29W128GL Table 11. Standard commands, 16-bit mode Bus operations(1) Command Length 1st Add 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto Select block protection indicator Block protection status Program(4) Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 6 6+ 1 1 1 555 555 555 X X 55 AA AA AA B0 30 98 2AA 2AA 2AA 55 55 55 555 555 555 A0 80 80 PA 555 555 PD AA AA 3 555 AA 2AA 55 555 90 (2)(3) (2)(3) Command interface 2nd Data Add Data F0 AA 2AA 55 X 3rd Add 4th 5th 6th Data Add Data Add Data Add Data X 555 F0 2AA 2AA 55 55 555 BAd 10 30 1. X Don't care, PA Program Address, PD Program Data, BAd any address in the Block. All values in the table are in hexadecimal. 2. These cells represent Read cycles. The other cells are Write cycles. 3. The Auto Select addresses and data are given in Table 7: Read electronic signature - auto select mode - programmer method (16-bit mode), and Table 9: Block protection - auto select mode - programmer method (16-bit mode), except for A9 that is `Don't care'. 4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 12 and Table 13 Fast Program commands, 8bit and 16-bit mode). 33/94 Command interface M29W128GH, M29W128GL 6.2 Fast Program commands The M29W128GH/L offers a set of Fast Program commands to improve the programming throughput: Write to Buffer Program Enhanced Buffered Program (valid in x 16 mode only) Unlock Bypass. See either Table 12, Table 13 or Table 14 depending on the configuration that is being used, for a summary of the Fast Program commands. When VPPH is applied to the VPP/Write Protect pin the memory automatically enters Unlock Bypass mode (see Section 6.2.6: Unlock Bypass command). After programming has started, Bus Read operations in the memory output the Status Register content. Write to Buffer Program command can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.8: Program Suspend command and Section 6.1.9: Program Resume command). After the fast program operation has completed, the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical program times are given in Table 17: Program, Erase times and Program, Erase endurance cycles. 6.2.1 Write to Buffer Program command The Write to Buffer Program command makes use of the device's 32-word/64-byte write buffer to speed up programming. 32 words/64 bytes can be loaded into the write buffer. Each write buffer has the same A22-A5 addresses.The Write to Buffer Program command dramatically reduces system programming time compared to the standard non-buffered Program command. When issuing a Write to Buffer Program command, the VPP/WP pin can be either held High, VIH, or raised to VPPH. See Table 17 for details on typical Write to Buffer Program times in both cases. Five successive steps are required to issue the Write to Buffer Program command: 1. 2. 3. The Write to Buffer Program command starts with two unlock cycles The third Bus Write cycle sets up the Write to Buffer Program command. The setup code can be addressed to any location within the targeted block The fourth Bus Write cycle sets up the number of words/bytes to be programmed. Value N is written to the same block address, where N+1 is the number of words/bytes to be programmed. N+1 must not exceed the size of the write buffer or the operation will abort The fifth cycle loads the first address and data to be programmed Use N Bus Write cycles to load the address and data for each word/byte into the write buffer. Addresses must lie within the range from the start address+1 to the start address + N-1. Optimum performance is obtained when the start address corresponds 4. 5. 34/94 M29W128GH, M29W128GL Command interface to a 32-word/64-byte boundary. If the start address is not aligned to a 32-word/64-byte boundary, the total programming time is doubled. All the addresses used in the Write to Buffer Program operation must lie within the same page. To program the content of the write buffer, this command must be followed by a Write to Buffer Program Confirm command. If an address is written several times during a Write to Buffer Program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write to Buffer Program. The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a Write to Buffer Program operation. It is possible to detect Program operation fails when changing programmed data from `0' to `1', that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. See Appendix D, Figure 28: Write to Buffer Program flowchart and pseudocode, for a suggested flowchart on using the Write to Buffer Program command. 6.2.2 Enhanced Buffered Program command The Enhanced Buffered Program command, available only in x 16 mode, makes use of the device's 256-word write buffer to speed up programming. 256 words can be loaded into the write buffer. Each write buffer has the same A22-A8 addresses. The Enhanced Buffered Program command dramatically reduces system programming time compared to both the standard non-buffered Program command and the Write to Buffer command. When issuing an Enhanced Buffered Program command, the VPP/WP pin can be either held High, VIH, or raised to VPPH. See Table 17: Program, Erase times and Program, Erase endurance cycles for details on typical Enhanced Buffered Program times in both cases. Three successive steps are required to issue the Enhanced Buffered Program command: The Enhanced Buffered Program command starts with two unlock cycles The third Bus Write cycle sets up the Enhanced Buffered Program command. The setup code can be addressed to any location within the targeted block The fourth Bus Write cycle loads the first address and data to be programmed. There a total of 256 address and data loading cycles. To program the content of the write buffer, the Enhanced Buffered Program command must be followed by an Enhanced Buffered Program Confirm command. The command ends with an internal Enhanced Buffered Program Confirm cycle. Note that address/data cycles must be loaded in an increasing address order (from ADD[7:0]=00000000 to ADD[7:0]=11111111) and completely (all 256 words). Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Enhanced Buffered Program. The Status Register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status during an Enhanced Buffered Program operation. 35/94 Command interface M29W128GH, M29W128GL An external supply (12 V) can be used to improve programming efficiency. It is possible to detect Program operation fails when changing programmed data from `0' to `1', that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous and the current value. See Appendix D and Figure 29: Enhanced Buffered Program flowchart and pseudocode, for a suggested flowchart on using the Enhanced Buffered Program command. 6.2.3 Buffered Program Abort and Reset command A Buffered Program Abort and Reset command must be issued to abort the Write to Buffer Program and Enhanced Buffered Program operation and reset the device in Read mode. The write to buffer and enhanced buffered programming sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the number of locations to program step in the Write to Buffer Program command Write to an address in a block different than the one specified during the write-bufferload command Write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation Write data other than the Confirm command after the specified number of data load cycles Load address/data pairs in an incorrect sequence during the enhanced buffered program. The abort condition is indicated by DQ1 = 1, DQ7 = DQ7 (for the last address location loaded), DQ6 = toggle, and DQ5 = 0 (all of which are Status Register bits). A Buffered Program Abort and Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Buffered Program Abort and Reset command sequence is required when using write to buffer and enhanced buffered programming features in Unlock Bypass mode. Note: Enhanced Buffered Program commands are available for x 16 mode only. 36/94 M29W128GH, M29W128GL Command interface 6.2.4 Write to Buffer Program Confirm command The Write to Buffer Program Confirm command is used to confirm a Write to Buffer Program command and to program the N+1 words/bytes loaded in the write buffer by this command. 6.2.5 Enhanced Buffered Program Confirm command The Enhanced Buffered Program Confirm command is used to confirm an Enhanced Buffered Program command and to program the 256 words loaded in the buffer. 6.2.6 Unlock Bypass command The Unlock Bypass command is used to place the device in Unlock Bypass mode. When the device enters the Unlock Bypass mode, the two initial unlock cycles required in the standard program command sequence are no more needed, and only two write cycles are required to program data, instead of the normal four cycles (see Note 4 below Table 10 and Table 11). This results in a faster total programming time. Unlock Bypass command is consequently used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. When in Unlock Bypass mode, only the Unlock Bypass Program, Unlock Bypass Block Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid: The Unlock Bypass Program command can be issued to program addresses within the memory The Unlock Bypass Block Erase command can then be issued to erase one or more memory blocks The Unlock Bypass Chip Erase command can be issued to erase the whole memory array The Unlock Bypass Write to Buffer Program command can be issued to speed up programming operation The Unlock Bypass Enhanced Buffered Program command can be issued to speed up programming operation The Unlock Bypass Reset command can be issued to return the memory to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. 6.2.7 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the memory outputs the Status Register. See the Program command for details on the behavior. 37/94 Command interface M29W128GH, M29W128GL 6.2.8 Unlock Bypass Block Erase command The Unlock Bypass Block Erase command can be used to Erase one or more memory blocks at a time. The command requires two Bus Write operations instead of six using the standard Block Erase command. The final Bus Write operation latches the address of the block and starts the Program/Erase controller. To erase multiple block (after the first two Bus Write operations have selected the first block in the list), each additional block in the list can be selected by repeating the second Bus Write operation using the address of the additional block. The Unlock Bypass Block Erase command behaves in the same way as the Block Erase command: the operation cannot be aborted, and a Bus Read operation to the memory outputs the Status Register (see Section 6.1.5: Block Erase command for details). 6.2.9 Unlock Bypass Chip Erase command The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time. The command requires two Bus Write operations only instead of six using the standard Chip Erase command. The final Bus Write operation starts the Program/Erase controller. The Unlock Bypass Chip Erase command behaves in the same way as the Chip Erase command: the operation cannot be aborted, and a Bus Read operation to the memory outputs the Status Register (see Section 6.1.4: Chip Erase command for details). 6.2.10 Unlock Bypass Write to Buffer Program command The Unlock Bypass Write to Buffer command can be used to program the memory in Fast Program mode. The command requires two Bus Write operations less than the standard Write to Buffer Program command. The Unlock Bypass Write to Buffer Program command behaves in the same way as the Write to Buffer Program command: the operation cannot be aborted and a Bus Read operation to the memory outputs the Status Register (see Section 6.2.1: Write to Buffer Program command for details). The Write to Buffer Program Confirm command is used to confirm an Unlock Bypass Write to Buffer Program command and to program the N+1 words/bytes loaded in the write buffer by this command. 6.2.11 Unlock Bypass Enhanced Buffered Program command The Unlock Bypass Enhanced Buffered Program command can be used to program the memory in Fast Program mode. The command requires two address/data loading cycles less than the standard Enhanced Buffered Program command (see Table 14: Enhanced Buffered Program commands, 16-bit mode). The Unlock Bypass Enhanced Buffered Program command behaves identically to the Enhanced Buffered Program operation using the Enhanced Buffered Program command. The operation cannot be aborted and a Bus Read operation to the memory outputs the Status Register (see Section 6.2.2: Enhanced Buffered Program command for details on the behavior). The Enhanced Buffered Program Confirm command is used to confirm an Unlock Bypass Enhanced Buffered Program command and to program the 256 words loaded in the buffer. 38/94 M29W128GH, M29W128GL Command interface 6.2.12 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode. 39/94 Command interface Table 12. Fast Program commands, 8-bit mode Length Bus Write operations(1) 1st Add 2nd Data 3rd Add Data 4th Add Data 5th Add Data 6th Add Data M29W128GH, M29W128GL Command 7th 8th 9th Data Data Add Add Data Add Data Add Write to Buffer Program Write to Buffer Program Confirm Buffered Program Abort and Reset Unlock Bypass Unlock Bypass Program Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Write to Buffer Program Unlock Bypass Reset 1. 2. 3. 4. 5. N+5 AAA AA 555 55 BAd 25 BAd N(2) PA(3) PD WBL (4) PD 1 BAd (5) 29 3 AAA AA 555 55 AAA F0 3 AAA AA 555 55 AAA 20 2 X A0 PA PD 2+ X 80 BAd 30 2 X 80 X 10 N+3 BAd 25 BAd N(2) PA (3) PD WBL (6) PD 2 X 90 X 00 X Don't care, PA Program Address, PD Program Data, BAd Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer Program operation. Each buffer has the same A22-A5 addresses. A0-A4 and A-1 are used to select a byte within the N+1 byte page. The 6th cycle has to be issued N time. WBL scans the word inside the page. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles. 6. The 4th cycle has to be issued N time. WBL scans the word inside the page. 40/94 M29W128GH, M29W128GL Table 13. Fast Program commands, 16-bit mode Bus Write operations(1) Length Command 1st Add Write to Buffer Program Write to Buffer Program Confirm Buffered Program Abort and Reset Unlock Bypass Unlock Bypass Program Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Write to Buffer Program Unlock Bypass Reset N+5 1 3 3 2 2+ 2 555 BAd (5) Command interface 2nd Add 2AA Data 55 3rd Add BAd Data 25 4th Add BAd Data N(2) 5th Add PA(3) Data PD 6th Add WBL (4) Data AA 29 AA AA A0 80 80 Data PD 555 555 X X X 2AA 2AA PA BAd X 55 55 PD 30 10 555 555 F0 20 N+3 BAd 25 BAd N(2) PA (3) PD WBL (6) PD 2 X 90 X 00 1. X Don't care, PA Program Address, PD Program Data, BAd Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the Write to Buffer Program operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles. Table 14. Length Enhanced Buffered Program commands, 16-bit mode(1) Bus Write operations Command 1st Add Data 2nd Add 3rd 4th Add ... Data 257th Add Data 258th Add Data 259th Add BAd (FF) Data 260th Add Data Data Add Data Add Data BAd (00) Enhanced Buffered Program Enhanced Buffered Program Confirm Unlock Bypass Enhanced Buffered Program 259 555 AA 2AA 55 BAd 33 Data ... ... Data 1 BAd (00) 29 257 BAd 33 BAd (00) Data BAd (FF) Data 1. Only available from week 8 of 2008. 41/94 Command interface M29W128GH, M29W128GL 6.3 Protection commands Blocks can be protected individually against accidental program, erase or read operations. The device block protection scheme is shown in Figure 5: Software protection scheme. See either Table 15, or Table 16, depending on the configuration that is being used, for a summary of the Block Protection commands. Block protection commands are available both in 8-bit and 16-bit configuration. The memory block and Extended Memory block protection is configured through the Lock register (see Section 7.1: Lock Register). 6.3.1 Enter Extended Memory Block command The M29W128GH/L has one extra 128-word block (extended memory block) that can only be accessed using the Enter Extended Memory Block command. Three Bus Write cycles are required to issue the Extended Memory Block command. Once the command has been issued the device enters the Extended Memory Block mode where all Bus Read or Program operations are conducted on the extended memory block. Once the device is in the Extended Block mode, the extended memory block is addressed by using the addresses occupied by block 0 in the other operating modes (see Table 34: Block addresses). The device remains in Extended Memory Block mode until the Exit Extended Memory Block command is issued or power is removed from the device. After power-up or a hardware reset, the device reverts to the Read mode, and the commands issued to block 0 addresses will properly address block 0. The extended memory block cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase Resume commands are not allowed. To exit from the Extended Memory Block mode the Exit Extended Memory Block command must be issued. The Extended Memory Block can be protected by setting the Extended Memory Block Protection bit to `1' (see Section 7.1: Lock Register); however once protected the protection cannot be undone. Note: When the device is in the Extended Memory Block mode, the VPP/WP pin cannot be used for fast programming and the Unlock Bypass mode is not available (see Section 2.8: VPP/Write Protect (VPP/WP)). 6.3.2 Exit Extended Memory Block command The Exit Extended Memory Block command is used to exit from the Extended Memory Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. 42/94 M29W128GH, M29W128GL Command interface 6.3.3 Lock Register command set The M29W128GL and M29W128GH offer a set of commands to access the Lock Register and to configure and verify its content. See the following sections in conjunction with Section 7.1: Lock Register, Table 15 and Table 16. Enter Lock Register Command Set command Three Bus Write cycles are required to issue the Enter Lock Register Command Set command. Once the command has been issued, all Bus Read or Program operations are issued to the Lock Register. Lock Register Program and Lock Register Read command The Lock Register Program command allows to configure the Lock Register. The programmed data can then be checked by issuing a Lock Register Read command. An Exit Protection Command Set command must then be issued to return the device to Read mode (see Section 6.3.8: Exit Protection command set). 6.3.4 Password Protection mode command set Enter Password Protection Command Set command Three Bus Write cycles are required to issue the Enter Password Protection Command Set command. Once the command has been issued, the commands related to the Password Protection mode can be issued to the device. Password Program command The Password Program command is used to program the 64-bit password used in the Password Protection mode. To program the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus DQ15A-1 in 8-bit mode, or four times at four consecutive addresses selected by A1-A0 in 16-bit mode. The password can be checked by issuing a Password Read command. Once Password Program operation has completed, an Exit Protection Command Set command must be issued to return the device to Read mode. The Password Protection mode can then be selected. By default, all Password bits are set to `1'. Password Read command The Password Read command is used to verify the Password used in Password Protection mode. To verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus DQ15A-1 in 8-bit mode, or four times at four consecutive addresses selected by A1-A0 in 16-bit mode. If the Password Mode Lock bit is programmed and the user attempts to read the password, the device will output FFh onto the I/O data bus. An Exit Protection Command Set command must be issued to return the device to Read mode. 43/94 Command interface M29W128GH, M29W128GL Password Unlock command The Password Unlock command is used to clear the NVPB Lock bit allowing to modify the NVPBs. The Password Unlock command must be issued along with the correct password. There must be a 1 s delay between successive Password Unlock commands in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. If this delay is not respected, the latest command will be ignored. Approximately 1 s is required for unlocking the device after the valid 64-bit password has been provided. 6.3.5 Non-volatile Protection mode command set Enter Non-volatile Protection Command Set command Three Bus Write cycles are required to issue the Enter Non-volatile Protection Command Set command. Once the command has been issued, the commands related to the NonVolatile Protection mode can be issued to the device. Non-volatile Protection Bit Program command (NVPB Program) A block can be protected from program or erase by issuing a Non-volatile Protection Bit command along with the block address. This command sets the NVPB to `1' for a given block. Read Non-volatile Protection Bit Status command (Read NVPB Status) The status of a NVPB for a given block or group of blocks can be read by issuing a Read Non-Volatile Modify Protection Bit command along with the block address. Clear all Non-volatile Protection Bits command (Clear all NVPBs) The NVPBs are erased simultaneously by issuing a Clear all Non-volatile Protection Bits command. No specific block address is required. If the NVPB Lock bit is set to `0', the command fails. 44/94 M29W128GH, M29W128GL Figure 6. NVPB Program/Erase algorithm Command interface Enter NVPB command set. Program NVPB Addr = BAd Read Byte twice Addr = BAd DQ6= Toggle YES NO NO DQ5=1 YES Wait 500 ms Read Byte twice Addr = BAd DQ6= Toggle NO Read Byte twice Addr = BAd NO DQ0= '1'(Erase) '0'(Program) Fail YES Reset Pass Exit NVPB command set AI14242 45/94 Command interface M29W128GH, M29W128GL 6.3.6 NVPB Lock Bit command set Enter NVPB Lock Bit Command Set command Three bus Write cycles are required to issue the Enter NVPB Lock Bit Command Set command. Once the command has been issued, the commands allowing to set the NVPB Lock bit can be issued to the device. NVPB Lock Bit Program command This command is used to set the NVPB Lock bit to `0' thus locking the NVPBs, and preventing them from being modified. Read NVPB Lock Bit Status command This command is used to read the status of the NVPB Lock bit. 6.3.7 Volatile Protection mode command set Enter Volatile Protection Command Set command Three bus Write cycles are required to issue the Enter Volatile Protection Command Set command. Once the command has been issued, the commands related to the Volatile Protection mode can be issued to the device. Volatile Protection Bit Program command (VPB Program) The VPB Program command individually sets a VPB to `0' for a given block. If the NVPB for the same block is set, the block is locked regardless of the value of the VPB bit. (see Table 19: Block protection status). Read VPB Status command The status of a VPB for a given block can be read by issuing a Read VPB Status command along with the block address. VPB Clear command The VPB Clear command individually clears (sets to `1') the VPB for a given block. If the NVPB for the same block is set, the block is locked regardless of the value of the VPB bit. (see Table 19: Block protection status). 6.3.8 Exit Protection command set The Exit Protection Command Set command is used to exit from the Lock Register, Password Protection, Non-Volatile Protection, Volatile Protection, and NVPB Lock Bit Command Set mode. It return the device to Read mode. 46/94 M29W128GH, M29W128GL Table 15. Block Protection commands, 8-bit mode(1)(2)(3) Bus operations Command Length 1st Ad Enter Lock Register Command Set(4) Lock Register Program Lock Register Read Enter Password Protection Command Set(4) Password Program (6)(7) Password Read Password Unlock(7) Enter NonVolatile Protection Command Set(4) NVPB Program(8) Clear all NVPBs(9) Read NVPB Status (8) Enter NVPB Lock Bit Command Set NVPB Lock Bit Program(8) Read NVPB Lock Bit Status (8) Enter Volatile Protection Command Set VPB Program(8) Read VPB Status VPB Clear(8) Exit Protection Command Set (10) Command interface 2nd Ad Data Ad 3rd Data Ad 4th Data Ad 5th Data Ad 6th Data Ad 7th Data Ad 8th Data Ad 9th Data 10th Ad Data 11th Ad Data Data Lock Register 3 AAA AA 555 55 AAA 40 2 X A0 DATA (5) X DATA (5) 1 X 3 AAA AA 555 55 AAA 60 Password Protection 2 X A0 PWD 0 25 PWA n 01 PWD n PWD 1 03 02 PWD 2 PWD 0 03 PWD 3 PWD 1 04 PWD 4 PWD 2 05 PWD 5 PWD 3 06 PWD 6 PWD 4 07 PWD 7 PWD 5 06 PWD 6 07 PWD 7 00 29 8 1 1 00 00 00 00 01 02 03 04 05 Non-volatile Protection 3 AAA AA 555 55 AAA C0 2 X A0 BAd 00 2 X 80 00 30 1 BAd RD(0) 3 AAA AA 555 55 AAA 50 NVPB Lock bit 2 X A0 X 00 1 X RD(0) 3 AAA AA 555 55 AAA E0 Volatile Protection 2 X A0 BAd 00 1 2 X X RD(0) A0 BAd 01 2 X 90 X 00 Enter Extended Block(4) Exit Extended Block 1. 3 AAA AA 555 55 AAA 88 4 AAA AA 555 55 AAA 90 X 00 Ad address, Dat data, BAd Any address in the Block, RD Read data, PWDn Password byte 0 to 7, PWAn Password Address (n = 0 to 7), X Don't care. All values in the table are in hexadecimal. 47/94 Command interface M29W128GH, M29W128GL 2. 3. 4. 5. 6. 7. 8. 9. Grey cells represent Read cycles. The other cells are Write cycles. DQ15 to DQ8 are `Don't care' during unlock and command cycles. A22 to A16 are `Don't care' during unlock and command cycles unless an address is required. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any other block are allowed. DATA = Lock Register content. Only one portion of password can be programmed or read by each Password Program command. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. Protected and unprotected states correspond to 00 and 01, respectively. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared Non Volatile Modify Protection bits. 10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to Read mode. 48/94 M29W128GH, M29W128GL Table 16. Block Protection commands, 16-bit mode(1)(2)(3) Bus operations Length Command 1st Ad Enter Lock Register Command Set(4) Lock Register Program Lock Register Read Password Protection Enter Password Protection Command Set(4) Password Program (6)(7) Password Read Password Unlock(7) 3 2 1 555 X X Data AA A0 DATA (5) Command interface 2nd Ad 2AA X Data 55 DATA (5) 3rd Ad 555 Data 40 Ad 4th Data Ad 5th Data Ad 6th Data Ad 7th Data Lock register 3 2 4 7 3 2 2 1 3 2 1 3 2 1 2 2 3 4 555 X 00 00 555 X X BAd 555 X X 555 X X X X 555 555 AA A0 PWD0 25 AA A0 80 RD(0) AA A0 RD(0) AA A0 RD(0) A0 90 AA AA 2AA PWAn 01 00 2AA BAd 00 55 PWDn PWD1 03 55 00 30 555 60 02 00 555 PWD2 PWD0 C0 03 01 PWD3 PWD1 02 PWD2 03 PWD3 00 29 Non-Volatile Protection NVPB Lock bit Enter Non-volatile Protection Command Set(4) NVPB Program(8) Clear all NVPBs(9) Read NVPB Status Enter NVPB Lock Bit Command Set NVPB Lock Bit Program Read NVPB Lock Bit Status Enter Volatile Protection Command Set VPB Program Read VPB Status VPB Clear 2AA X 55 00 555 50 Volatile Protection 2AA BAd 55 00 555 E0 BAd X 2AA 2AA 01 00 55 55 555 555 88 90 X 00 Exit Protection Command Set(10) Enter Extended Block(4) Exit Extended Block 1. 2. 3. 4. 5. 6. 7. 8. 9. Ad address, Dat data, BAd Any address in the Block, RD Read data, PWDn Password word 0 to 3, PWAn Password Address (n = 0 to 3), X Don't care. All values in the table are in hexadecimal. Grey cells represent Read cycles. The other cells are Write cycles. DQ15 to DQ8 are `Don't care' during unlock and command cycles. A22 to A16 are `Don't care' during unlock and command cycles unless an address is required. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any other block are allowed. DATA = Lock Register content. Only one portion of password can be programmed or read by each Password Program command. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. Protected and unprotected states correspond to 00 and 01, respectively. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared Non-volatile Modify Protection bits. 10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to Read mode. 49/94 Command interface Table 17. M29W128GH, M29W128GL Program, Erase times and Program, Erase endurance cycles Parameter Min Typ(1)(2) 40 0.5 25 50 Single Byte Program 16 VPP/WP = VPPH VPP/WP = VIH 51 78 16 VPP/WP = VPPH VPP/WP = VIH 51 78 270 135 Program)(5) 20 13 8 VPP)(5) 5 5 100,000 20 800(3) 400 (3) Max(2) 400 (3) Unit s s Chip Erase Block Erase (128 kbytes)(4) Erase Suspend latency time Block Erase timeout 35 s s s Byte Program Write to Buffer Program (64 bytes at-a-time) Single Word Program 200(3) s s 200(3) s s s s s s s s Cycles Years Word Program Write to Buffer Program (32 words at-a-time) Chip Program (byte by byte) Chip Program (word by word) Chip Program (Write to Buffer 200(3) 50(3) 40 25 15 Chip Program (Write to Buffer Program with VPP/WP = VPPH)(5) Chip Program (Enhanced Buffered Program) (5) Chip Program (Enhanced Buffered Program with VPP/WP = Program Suspend latency time Program/Erase cycles (per block) Data retention 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles. 4. Block Erase Polling cycle time (seeFigure 24: Data polling AC waveforms). 5. Intrinsic program timing, that means without the time required to execute the bus cycles to load the program commands. 50/94 M29W128GH, M29W128GL Registers 7 Registers The device feature two registers: A Lock Register that allows to configure the memory blocks and extended memory block protection (see Table 19: Block protection status) A Status Register that provides information on the current or previous Program or Erase operations. 7.1 Lock Register The Lock Register is a 16-bit one-time programmable register. The bits in the Lock Register are summarized in Table 18: Lock Register bits. See Section 6.3.3: Lock Register command set for a description of the commands allowing to read and program the Lock Register. 7.1.1 Password Protection Mode Lock bit (DQ2) The Password Protection Mode Lock bit, DQ0, is one-time programmable. Programming (setting to `0') this bit permanently places the device in Password Protection mode. Any attempt to program the Password Protection mode Lock bit when the Non-volatile Protection Mode bit is programmed causes the operation to abort and the device to return to Read mode. 7.1.2 Non-volatile Protection Mode Lock bit (DQ1) The Non-volatile Protection Mode Lock bit, DQ1, is one-time programmable. Programming (setting to `0') this bit permanently places the device in Non-volatile Protection mode. When shipped from the factory, all parts default to operate in Non-volatile Protection mode. The memory blocks can be either unprotected (NVPBs set to `1') or protected (NVPBs set to `0'), according to the ordering option that has been chosen. Any attempt to program the Non-volatile Protection mode Lock bit when the Password Protection Mode bit is programmed causes the operation to abort and the device to return to Read mode. 7.1.3 Extended Block Protection bit (DQ0) If the device has not been shipped with the extended memory block factory locked, the block can be protected by setting the Extended Memory Block Protection bit, DQ0, to `0'. However, this bit is one-time programmable and once protected the extended memory block cannot be unprotected. The extended memory block protection status can be read in Auto Select mode either by applying VID to A9 (see Table 8 and Table 9) or by issuing an Auto Select command (see Table 10 and Table 11). 7.1.4 DQ15 to DQ3 reserved They are `Don't care'. 51/94 Registers Table 18. Lock Register bits(1) DQ2 Password Protection Mode Lock bit DQ1 M29W128GH, M29W128GL DQ15-3 Don't care DQ0 Extended Block Protection bit Non-volatile Protection Mode Lock bit 1. DQ0, DQ1 and DQ2 Lock Register bits are set to `1' when shipped from the factory. Table 19. Block protection status Block NVPB(2) 0 1 1 0 1 1 Block VPB(3) x 1 0 x 0 1 Block protection status 01h 00h 00h 01h 01h 00h Block protection status Block protected (non-volatile protection through NVPB) Block unprotected Block protected (volatile protection through VPB) Block protected (non-volatile protection through NVPB) Block protected (volatile protection through VPB) Block unprotected NVPB Lock bit(1) 0 0 0 1 1 1 1. If the NVPB Lock bit is set to `0', all NVPBs are locked. If the NVPB Lock bit is set to `1', all NVPBs are unlocked. 2. If the Block NVPB is set to `0', the block is protected, if set to `1', it is unprotected. 3. If the Block VPB is set to `0', the block is protected, if set to `1', it is unprotected. 52/94 M29W128GH, M29W128GL Figure 7. Lock Register program flowchart Registers START Write Unlock cycles: Add 555h, Data AAh Add 2AAh, Data 55h Unlock cycle 1 unlock cycle 2 Write Enter Lock Register command set: Add 555h, Data 40h Program Lock Register Data: Add Dont' care, Data A0h Add Dont' care(1), Data PDh Polling algorithm YES Done NO DQ5 = 1 NO YES Device returned to Read mode PASS: Write Lock Register Exit command: Add Dont' care, Data 90h Add Dont' care, Data 00h FAIL Reset to return the device to Read mode ai13677 1. PD is the programmed data (see Table 18: Lock Register bits). 2. The Lock Register can only be programmed once. 53/94 Registers M29W128GH, M29W128GL 7.2 Status Register The M29W128GH/L has one Status Register. The various bits convey information and errors on the current and previous program/erase operation. Bus Read operations from any address within the memory, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 20: Status Register bits. 7.2.1 Data Polling bit (DQ7) The Data Polling bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations, from the address just programmed, output DQ7, not its complement. During Erase operations the Data Polling bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling bit will change from '0' to '1' when the Program/Erase controller has suspended the Erase operation. Figure 8: Data polling flowchart, gives an example of how to use the Data Polling bit. A Valid Address is the address being programmed or an address within the block being erased. 7.2.2 Toggle bit (DQ6) The Toggle bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle bit is output on DQ6 when the Status Register is read. During a Program/Erase operation the Toggle bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle bit will output when addressing a cell within a block being erased. The Toggle bit will stop toggling when the Program/Erase controller has suspended the Erase operation. Figure 9: Toggle flowchart, gives an example of how to use the Data Toggle bit. 7.2.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase controller. The Error bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued 54/94 M29W128GH, M29W128GL Registers before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. 7.2.4 Erase Timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase controller operation during a Block Erase command. Once the Program/Erase controller starts erasing the Erase Timer bit is set to '1'. Before the Program/Erase controller starts the Erase Timer bit is set to '0' and additional blocks to be erased may be written to the command interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 7.2.5 Alternative Toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory array data as if in Read mode. After an Erase operation that causes the Error bit to be set, the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. 7.3 Buffered Program Abort bit (DQ1) The Buffered Program Abort bit, DQ1, is set to `1' when a Write to Buffer Program or Enhanced Buffered Program operation aborts. The Buffered Program Abort and Reset command must be issued to return the device to Read mode (see Write to Buffer Program in Section 6.1: Standard commands). 55/94 Registers Table 20. Status Register bits(1) Operation Program(2) Program During Erase Suspend Buffered Program Abort Program Error Chip Erase (2) M29W128GH, M29W128GL Address Any address Any address Any address Any address Any address Erasing block DQ7 DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 DQ3 0 0 0 1 0 0 0 0 0 0 - - - - 1 0 0 1 1 - DQ2 - - - - Toggle Toggle No toggle Toggle No toggle Toggle DQ1 0 - 1 - - - - - - - - RB 0 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Block Erase before timeout Non-erasing block Erasing block Block Erase Non-erasing block Erasing block Erase Suspend Non-erasing block Good block address Erase Error Faulty Block address 1. Unspecified data bits should be ignored. 2. DQ7 for Write to Buffer Program and Enhanced Buffered Program is related to the last address location loaded. Data read as normal 0 0 Toggle Toggle 1 1 1 1 No toggle Toggle - - 56/94 M29W128GH, M29W128GL Figure 8. Data polling flowchart Registers START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO DQ5 = 1 YES YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI07760 57/94 Registers Figure 9. Toggle flowchart START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address M29W128GH, M29W128GL DQ6 = TOGGLE YES NO DQ5 =1 YES NO READ DQ6 TWICE at Valid Address DQ6 = TOGGLE YES FAIL NO PASS AI11530 58/94 M29W128GH, M29W128GL Maximum ratings 8 Maximum ratings Stressing the device above the rating listed in Table 21: Absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 21. Symbol TBIAS TSTG VIO VCC VCCQ VID VPPH(3) Absolute maximum ratings Parameter Temperature under bias Storage temperature Input or output Supply voltage Input/output supply voltage Identification voltage Program voltage voltage(1)(2) Min - 50 - 65 - 0.6 - 0.6 - 0.6 - 0.6 - 0.6 Max 125 150 VCC + 0.6 4 4 13.5 13.5 Unit C C V V V V V 1. Minimum voltage may undershoot to - V during transition and for less than 20 ns during transitions. 2 2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20 ns during transitions. 3. VPPH must not remain at 12 V for more than a total of 80 hrs. 59/94 DC and AC parameters M29W128GH, M29W128GL 9 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 22: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 22. Operating and AC measurement conditions M29W128GH, M29W128GL Parameter 70 or 60(1) ns Min VCC supply voltage VCCQ supply voltage (VCCQ VCC) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 1. Only available upon customer request. 80 ns Min 2.7 1.65 -40 30 Max 3.6 3.6 85 Unit Max 3.6 3.6 85 30 10 2.7 2.7 -40 V V C pF 10 0 to VCCQ VCCQ/2 ns V V 0 to VCCQ VCCQ/2 Figure 10. AC measurement load circuit VPP VCC VCCQ 25 k DEVICE UNDER TEST 25 k CL 0.1 F 0.1 F CL includes JIG capacitance AI05558b 60/94 M29W128GH, M29W128GL Figure 11. AC measurement I/O waveform VCCQ VCCQ/2 0V AI05557b DC and AC parameters Table 23. Symbol Power-up waiting timings Alt. Parameter M29W128GH, M29W128GL 70 or 60 (1) Unit ns 0 80 ns s s s s s tVCHVCQH tVCHRH(3) tVCQHRH tRHEL tRHWL (3) VCC tVCS tVIOS tRH (2) High to VCCQ(2) High Min Min Min Min Min VCC High to rising edge of RP VCCQ High to rising edge of RP RP High to Chip Enable Low RP High to Write Enable Low 35 0 50 500 1. Only available upon customer request. 2. VCC and VCCQ ramps must be synchronized during power-up. 3. If RP is not stable for tVCHRH or tVCQHRH, the device does not permit any Read and Write operations and a hardware reset is required. Figure 12. Power-up waiting timings tVCHVCQH VCC VCCQ tRHEL E tVCQHRH RP tVCHRH W tRHWL AI14247 61/94 DC and AC parameters Table 24. Device capacitance(1) Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V M29W128GH, M29W128GL Symbol CIN COUT Min Max 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 25. Symbol ILI(1) ILO DC characteristics Parameter Input leakage current Output leakage current Random Read Test condition 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIH, f = 6 MHz E = VIL, G = VIH, f = 10 MHz E = VCCQ 0.2 V, RP = VCCQ 0.2 V Program/Erase controller active VPP/WP = VIL or VIH VPP/WP = VPPH 1 1 1 1 3 1 - 0.5 0.7VCCQ Min Typ Max 1 1 10 15 100 20 20 5 5 10 5 10 5 0.3VCCQ VCCQ+0.4 0.15VCCQ 0.85VCCQ 11.5 11.4 2.3 12.5 12.6 2.5 Unit A A mA mA A ICC1 Read current Page Read ICC2 Supply current (Standby) ICC3(2) Supply current (Program/Erase) Read or Standby Program current (Program) Reset Program operation ongoing mA mA A A mA A mA A V V V V V V V IPP1 IPP2 IPP3 VPP/WP VCC RP = VSS 0.2 V VPP/WP = 12 V 5% VPP/WP = VCC VPP/WP = 12 V 5% VPP/WP = VCC VCC 2.7 V VCC 2.7 V IOL = 100 A, VCC = VCC(min), VCCQ = VCCQ(min) IOH = 100 A, VCC = VCC(min), VCCQ = VCCQ(min) IPP4 VIL VIH VOL VOH VID VPPH VLKO(2) Erase Program operation current (Erase) ongoing Input Low voltage Input High voltage Output Low voltage Output High voltage Identification voltage Voltage for VPP/WP Program acceleration Program/Erase lockout supply voltage 1. The maximum input leakage current is 5 A on the VPP/WP pin. 2. Sampled only, not 100% tested. 62/94 M29W128GH, M29W128GL Figure 13. Random Read AC waveforms (8-bit mode) DC and AC parameters tAVAV A0-A22/ A-1 tAVQV E tELQV tELQX G (8-bit mode) tGLQX tGLQV DQ0-DQ7 tBHQV BYTE tELBL/tELBH tBLQZ AI08970 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID Figure 14. Random Read AC waveforms (16-bit mode) tAVAV A0-A22 tAVQV E tELQV tELQX G (8-bit mode) tGLQX tGLQV DQ0-DQ14, DQ15A-1 tBHQV BYTE tELBL/tELBH tBLQZ AI13698 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID 63/94 64/94 VALID VALID VALID VALID VALID VALID VALID VALID VALID tEHQX tEHQZ tGLQV tAVQV1 VALID VALID VALID VALID VALID VALID VALID tGHQX tGHQZ VALID AI08971c DC and AC parameters A3-A22 A0-A2 tAVQV E Figure 15. Page Read AC waveforms (16-bit mode) tELQV G DQ0-DQ15 DQ15A-1 M29W128GH, M29W128GL M29W128GH, M29W128GL Table 26. Read AC characteristics DC and AC parameters M29W128GH, M29W128GL Symbol Alt. Parameter Test condition 60 ns(1) 70 ns VCCQ=VCC VCCQ=VCC 80 ns VCCQ=1.65 V to VCC 80 Unit tAVAV tRC Address Valid to Next Address Valid Address Valid to Output Valid Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition E = VIL , G = VIL Min 60 70 ns tAVQV tACC E = VIL , Max G = VIL E = VIL , Max G = VIL G = VIL Min 60 70 80 ns tAVQV1 tELQX(2) tELQV tGLQX(2) tGLQV tEHQZ(2) tGHQZ(2) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tPAGE 25 25 30 ns tLZ tE tOLZ tOE tHZ tDF 0 60 0 25 20 20 0 70 0 25 20 20 0 80 0 30 30 20 ns ns ns ns ns ns G = VIL Max E = VIL Min E = VIL Max G = VIL Max E = VIL Max tOH Min 0 0 0 ns tELFL Chip Enable to BYTE Low tELFH or High tFLQZ BYTE Low to Output Hi-Z tFHQV BYTE High to Output Valid Max Max Max 5 25 30 5 25 30 5 25 30 ns ns ns 1. Only available upon customer request. 2. Sampled only, not 100% tested. 65/94 DC and AC parameters Figure 16. Write Enable Controlled Program waveforms (8-bit mode) 3rd cycle tAVAV A0-A22/ A-1 555h tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 AOh PD tWHDX tWHWH1 DQ7 DOUT tWHWL tWHEH PA tWLAX PA 4th cycle Data Polling tAVAV M29W128GH, M29W128GL Read cycle tELQV tGLQV tGHQZ DOUT tAXQX AI13333 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. SeeTable 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable Controlled and Table 26: Read AC characteristics for details on the timings. 66/94 M29W128GH, M29W128GL Figure 17. Write Enable Controlled Program waveforms (16-bit mode) 3rd cycle tAVAV A0-A22 555h tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ1', DQ15A-1 AOh PD tWHDX tWHWH1 DQ7 DOUT tGHQZ tWHWL tWHEH PA tWLAX PA 4th cycle Data Polling tAVAV DC and AC parameters Read cycle tELQV tGLQV tAXQX DOUT AI13699 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. SeeTable 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable Controlled and Table 26: Read AC characteristics for details on the timings. 67/94 DC and AC parameters Table 27. Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL (2) M29W128GH, M29W128GL Write AC characteristics, Write Enable Controlled M29W128GH, M29W128GL Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 ns(1) 60 0 35 45 0 0 30 0 45 0 0 30 50 Unit 70 ns 70 0 35 45 0 0 30 0 45 0 0 30 50 80 ns 80 0 35 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s M tVCHEL 1. Only available upon customer request. 2. Sampled only, not 100% tested. 68/94 M29W128GH, M29W128GL Figure 18. Chip Enable Controlled Program waveforms (8-bit mode) 3rd cycle tAVAV A0-A22/ A-1 555h tAVEL tWLEL W tGHEL G tELEH E tDVEH DQ0-DQ7 AOh PD tEHDX tWHWH1 tEHEL1 tEHWH PA tELAX PA 4th cycle Data Polling DC and AC parameters DQ7 DOUT AI13334 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. See Table 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable Controlled and Table 26: Read AC characteristics for details on the timings. 69/94 DC and AC parameters Figure 19. Chip Enable Controlled Program waveforms (16-bit mode) 3rd cycle tAVAV A0-A22 555h tAVEL tWLEL W tGHEL G tELEH E tDVEH DQ0-DQ14 A-1 AOh PD tEHDX tWHWH1 tEHEL1 tEHWH PA tELAX PA 4th cycle Data Polling M29W128GH, M29W128GL DQ7 DOUT AI14100 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. See Table 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable Controlled and Table 26: Read AC characteristics for details on the timings. 70/94 M29W128GH, M29W128GL Figure 20. Chip/Block Erase waveforms (8-bit mode) DC and AC parameters tAVAV A0-A22/ A-1 555h tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 AAh 55h tWHDX AI13335 2AAh 555h tWLAX 555h 2AAh 555h/BAd (1) tWHEH tWHWL 80h AAh 55h 10h/ 30h 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a Block Erase command. 2. BAd is the block address. 3. See Table 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable Controlled and Table 26: Read AC characteristics for details on the timings. Table 28. Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL Write AC characteristics, Chip Enable Controlled M29W128GH, M29W128GL Alt. tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Min Min Min Min Min Min Min Min Min Min 60 ns(1) 60 0 35 45 0 0 30 0 45 0 Unit 70 ns 70 0 35 45 0 0 30 0 45 0 80 ns 80 0 35 45 0 0 30 0 45 0 ns ns ns ns ns ns ns ns ns ns 1. Only available upon customer request. 71/94 DC and AC parameters Figure 21. Reset AC waveforms (no program/erase ongoing) M29W128GH, M29W128GL RB E, G tPHEL, tPHGL RP tPLPX AI11300b Figure 22. Reset during program/erase operation AC waveforms tPLYH RB tRHEL, tRHGL E, G RP tPLPX AI11301b Table 29. Symbol Reset AC characteristics Alt. Parameter M29W128GH, M29W128GL 60(1) 70 50 10 50 10 50 0 80 50 10 50 10 50 0 s s ns s s ns Unit tPLYH(2) tPLPX tPHEL, tPHGL(2) tREADY RP Low to Read mode, during Program or Erase tRP tRH tRPD RP Pulse width RP High to Write Enable Low, Chip Enable Low, Output Enable Low RP Low to Standby mode, during Read mode Max Min Min Min 50 10 50 10 50 0 RP Low to Standby mode, during Program or Erase Min RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min tRHEL, tRHGL(2) tRB 1. Only available upon customer request. 2. Sampled only, not 100% tested. 72/94 M29W128GH, M29W128GL Figure 23. Accelerated program timing waveforms DC and AC parameters VPPH VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 Figure 24. Data polling AC waveforms tWHEH E tGLQV G tWHGL2 W tWHWH1 or tWHWH2 DQ7 DATA DQ7 DQ7= Valid data Hi-Z tELQV tEHQZ tGHQZ DQ6-DQ0 DATA tWHRL DQ6-DQ0= Output flag DQ6-DQ0= Valid data Hi-Z R/B AI13336c 1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed. 2. See Table 30: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 26: Read AC characteristics for details on the timings. 73/94 DC and AC parameters M29W128GH, M29W128GL Figure 25. Toggle/Alternative Toggle bit polling AC waveforms (8-bit mode) A0-A22/ A-1 tGHAX E tWHGL2 W tGHGL2 G tWHDX DQ6/DQ2 Data tWHRL R/B AI13337 tAXGL tEHAX tEHEL2 tAVEL tGHGL2 tGLQV Toggle Toggle tELQV Toggle Stop toggling Output Valid 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing Chip Erase or Block Erase command is completed. 2. See Table 30: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 26: Read AC characteristics for details on the timings. Table 30. Symbol Accelerated Program and Data Polling/Data Toggle AC characteristics Alt Parameter M29W128GH, M29W128GL 60(1) 70 250 10 10 10 20 30 80 250 10 10 10 20 30 ns ns ns ns ns ns Unit tVHVPP tAXGL tGHAX, tEHAX tEHEL2 tWHGL2, tGHGL2 tWHRL tASO tAHT tEPH tOEH VPP/WP raising and falling time Address setup time to Output Enable Low during Toggle bit polling Address hold time from Output Enable during Toggle bit polling Chip Enable High during Toggle bit polling Output Hold time during Data and Toggle bit polling Min Min Min Min Min Max 250 10 10 10 20 30 tBUSY Program/Erase Valid to RB Low 1. Only available upon customer request. 74/94 M29W128GH, M29W128GL Package mechanical 10 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. TSOP56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline 1 56 e D1 B 28 29 L1 A2 A E1 E DIE A1 C CP L TSOP-K 1. Drawing is not to scale. Table 31. TSOP56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data Millimeters Inches Max 1.20 0.10 1.00 0.22 0.05 0.95 0.17 0.10 0.15 1.05 0.27 0.21 0.10 14.00 20.00 18.40 0.50 0.60 3 13.90 19.80 18.30 - 0.50 0 14.10 20.20 18.50 - 0.70 5 0.551 0.787 0.724 0.020 0.024 3 0.547 0.780 0.720 - 0.020 0 0.004 0.039 0.009 0.002 0.037 0.007 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.004 0.555 0.795 0.728 - 0.028 5 Symbol Typ A A1 A2 B C CP D1 E E1 e L Min 75/94 Package mechanical M29W128GH, M29W128GL Figure 27. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline D FD FE D1 SD E E1 SE ddd BALL "A1" A e b A1 A2 BGA-Z23 1. Drawing is not to scale. Table 32. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data millimeters inches Max 1.20 0.30 0.80 0.35 10.00 7.000 9.90 - 0.50 10.10 - 0.10 1.00 13.00 7.00 1.50 3.00 0.50 0.50 - 12.90 - - - - - - 13.10 - - - - - 0.039 0.512 0.276 0.059 0.118 0.020 0.020 - 0.508 - - - - - 0.394 0.276 0.20 0.35 0.012 0.031 0.014 0.390 - 0.020 0.398 - 0.004 - 0.516 - - - - - 0.008 Typ Min Max 0.047 0.014 Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE Min 76/94 M29W128GH, M29W128GL Ordering information 11 Ordering information Table 33. Example: Ordering information scheme M29W128GH 70 N 6 F Device type M29 Operating voltage W = VCC = 2.7 to 3.6 V Device function 128GH = 128 Mbit (x 8/x 16), page, uniform block, Flash memory, highest block protected by VPP/WP 128GL = 128 Mbit (x 8/x 16), page, uniform block, Flash memory, lowest block protected by VPP/WP Speed 70 = 70 ns (80 ns if VCCQ = 1.65 V to VCC) 60 = 60 ns (80 ns if VCCQ = 1.65 V to VCC)(1) Package N = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x 13 mm, 1 mm pitch Temperature range 6 = -40 to 85 C Option E = ECOPACK package, standard packing F = ECOPACK package, tape & reel packing 1. Only available upon customer request. Note: This product is also available with the extended memory block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 77/94 Block addresses and read/modify protection groups M29W128GH, M29W128GL Appendix A Block addresses and read/modify protection groups Block addresses Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Block size (Kbytes/ Kwords) 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 8-bit address range (in hexadecimal) 0000000-001FFFF 0020000-003FFFF 0040000-005FFFF 0060000-007FFFF 0080000-009FFFF 00A0000-00BFFFF 00C0000-00DFFFF 00E0000-00FFFFF 0100000-011FFFF 0120000-013FFFF 0140000-015FFFF 0160000-017FFFF 0180000-019FFFF 01A0000-01BFFFF 01C0000-01DFFFF 01E0000-01FFFFF 0200000-021FFFF 0220000-023FFFF 0240000-025FFFF 0260000-027FFFF 0280000-029FFFF 02A0000-02BFFFF 02C0000-02DFFFF 02E0000-02FFFFF 0300000-031FFFF 0320000-033FFFF 0340000-035FFFF 0360000-037FFFF 0380000-039FFFF 03A0000-03BFFFF 16-bit address range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF Table 34. Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 78/94 M29W128GH, M29W128GL Table 34. Block 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Block addresses and read/modify protection groups Block addresses (continued) Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Block size (Kbytes/ Kwords) 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 8-bit address range (in hexadecimal) 03C0000-03DFFFF 03E0000-03FFFFF 0400000-041FFFF 0420000-043FFFF 0440000-045FFFF 0460000-047FFFF 0480000-049FFFF 04A0000-04BFFFF 04C0000-04DFFFF 04E0000-04FFFFF 0500000-051FFFF 0520000-053FFFF 0540000-055FFFF 0560000-057FFFF 0580000-059FFFF 05A0000-05BFFFF 05C0000-05DFFFF 05E0000-05FFFFF 0600000-061FFFF 0620000-063FFFF 0640000-065FFFF 0660000-067FFFF 0680000-069FFFF 06A0000-06BFFFF 06C0000-06DFFFF 06E0000-06FFFFF 0700000-071FFFF 0720000-073FFFF 0740000-075FFFF 0760000-077FFFF 0780000-079FFFF 07A0000-07BFFFF 07C0000-07DFFFF 16-bit address range (in hexadecimal) 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 79/94 Block addresses and read/modify protection groups Table 34. Block 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 M29W128GH, M29W128GL Block addresses (continued) Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Block size (Kbytes/ Kwords) 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 8-bit address range (in hexadecimal) 07E0000-07FFFFF 0800000-081FFFF 0820000-083FFFF 0840000-085FFFF 0860000-087FFFF 0880000-089FFFF 08A0000-08BFFFF 08C0000-08DFFFF 08E0000-08FFFFF 0900000-091FFFF 0920000-093FFFF 0940000-095FFFF 0960000-097FFFF 0980000-099FFFF 09A0000-09BFFFF 09C0000-09DFFFF 09E0000-09FFFFF 0A00000-0A1FFFF 0A20000-0A3FFFF 0A40000-0A5FFFF 0A60000-0A7FFFF 0A80000-0A9FFFF 0AA0000-0ABFFFF 0AC0000-0ADFFFF 0AE0000-0AFFFFF 0B00000-0B1FFFF 0B20000-0B3FFFF 0B40000-0B5FFFF 0B60000-0B7FFFF 0B80000-0B9FFFF 0BA0000-0BBFFFF 0BC0000-0BDFFFF 0BE0000-0BFFFFF 16-bit address range (in hexadecimal) 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 05F0000-05FFFFF 80/94 M29W128GH, M29W128GL Table 34. Block 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Block addresses and read/modify protection groups Block addresses (continued) Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Protection group Block size (Kbytes/ Kwords) 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 8-bit address range (in hexadecimal) 0C00000-0C1FFFF 0C20000-0C3FFFF 0C40000-0C5FFFF 0C60000-0C7FFFF 0C80000-0C9FFFF 0CA0000-0CBFFFF 0CC0000-0CDFFFF 0CE0000-0CFFFFF 0D00000-0D1FFFF 0D20000-0D3FFFF 0D40000-0D5FFFF 0D60000-0D7FFFF 0D80000-0D9FFFF 0DA0000-0DBFFFF 0DC0000-0DDFFFF 0DE0000-0DFFFFF 0E00000-0E1FFFF 0E20000-0E3FFFF 0E40000-0E5FFFF 0E60000-0E7FFFF 0E80000-0E9FFFF 0EA0000-0EBFFFF 0EC0000-0EDFFFF 0EE0000-0EFFFFF 0F00000-0F1FFFF 0F20000-0F3FFFF 0F40000-0F5FFFF 0F60000-0F7FFFF 0F80000-0F9FFFF 0FA0000-0FBFFFF 0FC0000-0FDFFFF 0FE0000-0FFFFFF 16-bit address range (in hexadecimal) 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 81/94 Common Flash interface (CFI) M29W128GH, M29W128GL Appendix B Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued, the memory enters Read CFI Query mode and read operations output the CFI data. Table 35, Table 36, Table 37, Table 38, Table 39 and Table 40 show the addresses (A-1, A0-A7) used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 40: Security code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 35. Address Sub-section name x 16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Security code area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the primary algorithm (optional) 64 bit unique device number Description Query structure overview(1) 1. Query data are always presented on the lowest order data outputs. Table 36. Address CFI query identification string(1) Data Description Value `Q' Query Unique ASCII String `QRY' `R' `Y' Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm Address for primary algorithm extended query table (see Table 39) AMD compatible P = 40h x 16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h Address for alternate algorithm extended query table 0000h NA Alternate vendor command set and control interface ID code second vendor - specified algorithm supported NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'. 82/94 M29W128GH, M29W128GL Table 37. CFI query system interface information(1) Data x 16 1Bh x8 36h 0027h Description Common Flash interface (CFI) Address Value VCC logic supply minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC logic supply maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VPPH [programming] supply minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPPH [programming] supply maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 10 mV Typical timeout for single byte/word program = 2n s Typical timeout for minimum size write buffer program = 2 s Typical timeout for individual block erase = 2 ms Typical timeout for full Chip Erase = 2n ms n n 2.7 V 1Ch 38h 0036h 3.6 V 1Dh 3Ah 00B5h 11.5 V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 00C5h 0004h 0004h 0009h 0010h 0004h 0002h 0003h 0004h 12.5 V 16 s 16 s 0.5 s 40 s 200 s 200 s 2.3 s 400 s Maximum timeout for byte/word program = 2n times typical Maximum timeout for write buffer program = 2 times typical Maximum timeout per individual block erase = n n 2n times typical Maximum timeout for Chip Erase = 2 times typical 1. The values given in the above table are valid for both packages. 83/94 Common Flash interface (CFI) Table 38. Device geometry definition Data x 16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0018h 0002h 0000h 0006h 0000h 0001h 007Fh 0000h 0000h 0002h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Device size = 2n in number of bytes Flash device interface code description Description M29W128GH, M29W128GL Address Value 16 Mbytes x 8, x 16 Async. 64 1 128 128 Kbytes Maximum number of bytes in multiple-byte program or page= 2n Number of Erase block regions. It specifies the number of regions containing contiguous Erase blocks of the same size. Erase block region 1 information Number of Erase blocks of identical size = 007Fh +1 Erase block region 1 information Block size in region 1 = 0200h * 256 byte Erase block region 2 information 0 Erase block region 3 information 0 Erase block region 4 information 0 84/94 M29W128GH, M29W128GL Table 39. Primary algorithm-specific extended query table (1) Data x 16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h 0052h 0049h 0031h 0033h 0010h Major version number, ASCII Minor version number, ASCII Address sensitive unlock (bits 1 to 0) 00 = required, 01= not required Silicon revision number (bits 7 to 2) Description Common Flash interface (CFI) Address Value `P' Primary algorithm extended query table unique ASCII string "PRI" `R' `I' `1' `3' Yes 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 0002h 0001h 0000h 0008h 0000h 0000h 0002h 00B5h Erase Suspend 00 = not supported, 01 = Read only, 02 = read and write Block protection 00 = not supported, x = number of blocks per group Temporary block unprotect 00 = not supported, 01 = supported Block protect /unprotect 06 = M29W128GH/M29W128GL Simultaneous operations: not supported Burst mode, 00 = not supported, 01 = supported Page mode, 00 = not supported, 02 = 8-word page VPPH supply minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPPH supply maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 2 1 Not supported 6 NA Not supported 02 11.5 V 4Eh 9Ch 00C5h 12.5 V Uniform + VPP/WP protecting highest or lowest block Supported 4Fh 9Eh 00xxh Top/bottom boot block flag xx = 04 = uniform device xx = 05 = top/bottom 50h A0h 0001h Program suspend, 00 = not supported, 01 = supported 1. The values given in the above table are valid for both packages. 85/94 Common Flash interface (CFI) Table 40. Security code area Data x 16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX M29W128GH, M29W128GL Address Description 86/94 M29W128GH, M29W128GL Extended memory block Appendix C Extended memory block The M29W128GH/L has an extra block, the extended memory block, that can be accessed using a dedicated command. This extended memory block is 128 words in x 16 mode and 256 bytes in x 8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The device can be shipped either with the extended memory block factory locked, or factory unlocked. If the extended memory block is not factory locked, it can be customer lockable. Its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the extended memory block is protected. When set to `0', it indicates that the device is customer lockable. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Memory Block Verify Indicator. It can be read in Auto Select mode using either the Programmer (see Table 8 and Table 9) or the Insystem method (see Table 10 and Table 11). The extended memory block can only be accessed when the device is in Extended Memory Block mode. For details of how the Extended Memory Block mode is entered and exited, refer to the Section 6.3.1: Enter Extended Memory Block command and Section 6.3.2: Exit Extended Memory Block command, and to Table 15 and Table 10. C.1 Factory locked extended memory block In devices where the extended memory block is factory locked, the security identification number is written to the extended memory block address space (see Table 41: Extended memory block address and data) in the factory. The DQ7 bit is set to `1' and the extended memory block cannot be unprotected. 87/94 Extended memory block M29W128GH, M29W128GL C.2 Customer lockable extended memory block A device where the extended memory block is customer lockable is delivered with the DQ7 bit set to `0' and the extended memory block unprotected. It is up to the customer to program and protect the extended memory block but care must be taken because the protection of the extended memory block is not reversible. If the device has not been shipped with the extended memory block factory protected, the block can be protected by setting the Extended Memory Block Protection bit, DQ0, to `0'. However, this bit is one-time programmable and once protected the extended memory block cannot be unprotected. Once the extended memory block is programmed, the Exit Extended Memory Block command must be issued to exit the Extended Memory Block mode and return the device to Read mode. Table 41. Extended memory block address and data Address(1) x8 000000h-0000FFh x 16 000000h-00007Fh Factory locked Security identification number Data Customer lockable Determined by customer 1. See Table 34: Block addresses. 88/94 M29W128GH, M29W128GL Flowcharts Appendix D Flowcharts Figure 28. Write to Buffer Program flowchart and pseudocode Start Write to Buffer command, block address Write n(1), block address First three cycles of the Write to Buffer and Program command Write Buffer Data, start address X=n X=0 NO Abort Write to Buffer NO YES YES Write to a different block address Write Next Data,(3) Program Address Pair Write to Buffer and Program Aborted(2) X = X-1 Write to Buffer Program Confirm, block address Read Status Register (DQ1, DQ5, DQ7) at last loaded address YES DQ7 = Data NO DQ1 = 1 YES NO NO DQ5 = 1 YES Check Status Register (DQ5, DQ7) at last loaded address DQ7 = Data (4) YES NO FAIL OR ABORT(5) END AI08968b 1. n+1 is the number of addresses to be programmed. 89/94 Flowcharts M29W128GH, M29W128GL 2. A Write to Buffer Program Abort and Reset must be issued to return the device in Read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However when loading write buffer address with data, all addresses must fall within the selected write buffer page. 4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 5. If this flowchart location is reached because DQ5='1', then the Write to Buffer Program command failed. If this flowchart location is reached because DQ1='1', then the Write to Buffer Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to Buffer Program Abort and Reset command if the operation aborted. 6. See Table 10 and Table 11, for details on Write to Buffer Program command sequence. 90/94 M29W128GH, M29W128GL Figure 29. Enhanced Buffered Program flowchart and pseudocode Start Enhanced Buffered Program command, block address Write Buffer Data, start address (00), X=255 YES Flowcharts First three cycles of the Enhanced Buffered Program command X=0 NO Abort Write to Buffer NO YES Write to a different block address Write Next Data,(2) Program Address Pair Enhanced Buffered Program Aborted(1) X = X-1 Enhanced Buffered Program Confirm, block address Read Status Register (DQ1, DQ5, DQ7) at last loaded address YES DQ7 = Data NO DQ1 = 1 YES NO NO DQ5 = 1 YES Check Status Register (DQ5, DQ7) at last loaded address DQ7 = Data (3) YES NO FAIL OR ABORT(4) END AI14243 1. A Buffered Program Abort and Reset must be issued to return the device in Read mode. 2. When the block address is specified, all the addresses in the selected block address space must be issued starting from (00). Furthermore, when loading write buffer address with data, data program addresses must be consecutive. 3. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 4. If this flowchart location is reached because DQ5='1', then the Enhanced Buffered Program command failed. If this flowchart location is reached because DQ1='1', then the Enhanced Buffered Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a 91/94 Flowcharts Buffered Program Abort and Reset command if the operation aborted. M29W128GH, M29W128GL 5. See Table 14: Enhanced Buffered Program commands, 16-bit mode, for details on Enhanced Buffered Program command sequence. 92/94 M29W128GH, M29W128GL Revision history 12 Revision history Table 42. Date 24-Nov-2006 Document revision history Version 0.1 Initial release. VIO changed to VCCQ in the whole document and added in Table 21: Absolute maximum ratings. Chip Program time without VPPH updated in Features section. RP signal acting as a Reset input, unprotection of all the blocks previously protected using a High Voltage Block Protection technique removed. Table 4: Bus operations, 8-bit mode and Table 5: Bus operations, 16-bit mode updated. Table 6: Read electronic signature - auto select mode programmer method (8-bit mode) and Table 7: Read electronic signature auto select mode - programmer method (16-bit mode) updated. Table 8: Block protection - auto select mode - programmer method (8-bit mode) and Table 9: Block protection - auto select mode - programmer method (16-bit mode) updated. Section 5: Software protection added, together with the related commands. Unlock Bypass Block Erase, Unlock Bypass Chip Erase, and Unlock Write to Buffer and Program commands added. Lock Register description added in Section 7.1. Enhanced Buffered Program commands added (see on page1 and from Section 6.2.2 to Section 6.2.12). Modified values for page access, random access, programming time, and chip program time on page 1. Speed classes changed in Table 27, Table 28, Table 29, Table 30, and Table 33. Table 14: Enhanced Buffered Program commands, 16-bit mode added. Table 12, Table 13, Table 15, Table 16, Table 17, Table 22, Table 26, Table 37, and Table 39 updated as well as Figure 22. Figure 29: Enhanced Buffered Program flowchart and pseudocode added in Appendix D. Document status promoted from preliminary data to datasheet. Speed classes and page size modified on page 1. Modified: Section 2.8: VPP/Write Protect (VPP/WP), Section 3.6: Automatic Standby, Section 6.1.5: Block Erase command, Table 3: VPP/WP functions, Table 22: Operating and AC measurement conditions, Table 25: DC characteristics, and Table 39: Primary algorithm-specific extended query table. Added: Table 23: Power-up waiting timings and Figure 12: Power-up waiting timings. Changed Erase Suspend latency time in Table 17: Program, Erase times and Program, Erase endurance cycles. Minor text changes. Applied Numonyx branding. Changes 30-Mar-2007 1 23-Oct-2007 2 28-Jan-2008 3 20-Mar-2008 4 93/94 M29W128GH, M29W128GL Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 94/94 |
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